Professor Roosta has over 38 years of academic and industrial experience in digital system design, FPGA/ASIC design and test, low power ASIC design,physical design automation, design for testability, and reliable microelectronics for Military & Space applications.

Dr. Roosta has also been a consultant for Caltech NASA/Jet Propulsion Laboratory (JPL), Teledyne System Company, Lockheed Martin, Northrop Grumman , Rockwell International, United Nations, and several other local and national industries.

Joined the Jet Propulsion Laboratory (JPL/NASA) in 2001 as a Senior Member of the Parts Engineering Group of the Electronic Parts Engineering Office. He served as a Member of the NASA Electronic Parts and Packaging (NEPP) Program. He was task manager on numerous R&D research projects sponsored by JPL, NEPP, and NASA Research and Technology Development (R&TD). Dr. Roosta has served as JPL representative to the Government-Industry Data Exchange Program (GIDEP) and JPL ALERT coordinator.

Recipient of several awards including; NASA Fellowship awards, NASA Group Achievement award , JPL Group Achievement award, IEEE distinguished Service award, IEEE Third Millennium Award, San Fernando Valley Engineers’ Council Outstanding Engineer Merit, and Distinguished Engineering Educator of the Year Award. Chair of the IEEE San Fernando Valley section for several years.

  • Ph.D. 1982, University of Southern California
  • M.A. 1978, University of Southern California
  • B.A. 1976, University of Tehran

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